Design for Test 2
Following your initial investigation into test equipment and its use you have become aware that increasing use of VLSI and SMT technology means that not all component faults can be detected with an In Circuit Tester. To improve this situation you have been advised to consider how effective testing can be achieved by making provision at the design stage. In particular you should:

? Partition complex circuits to reduce testing effort.

? Maximise access to inputs and outputs of complex devices so that the ICT can exert control and observe effects.

You already know that not all faults can be detected with one tester, hence your investigation into ICTs, MDAs and FTs. However, test equipment and its ongoing use cost money and it is important that testing is carried out economically as well as effectively. To specify capacities for your different testers will require more than knowledge of your overall unit throughput. You need to develop a test strategy that takes into account the effects of yield and ‘fault spectrum’ as well as purchase and running costs.

Guidance notes

Remember you do not necessarily have to solve the problem described. You do, however, need to understand and be able to explain how you would approach the problem.

Learning Outcomes

Following this PBL cycle you should be able to:

? Explain why design should take into account testing requirements.
? Discuss the use of partitioning to reduce test effort required.
? Describe methods for ensuring controllability and observability when designing circuits for test.
? Design an optimum test configuration (with equipment capacities) given information about product yield and fault spectrum.

Resources

Library Catalogue

? Automatic Test Equipment Brindley
? Testing Digital Circuits B.R.Wilkins
? Advanced Simulation &Test Methodologies for VLSI Russel & Sayers
? IEEE Standard 1149.1
? The Low Cost Board Test Handbook Craig Pynn
? Strategies for Electronic Test Craig Pynn
? Digital Board Testing Bennets
? Design to Test Turino

Internet
http://www.checksum.com/analyst_ft.html

Design for Test 2
Following your initial investigation into test equipment and its use you have become aware that increasing use of VLSI and SMT technology means that not all component faults can be detected with an In Circuit Tester. To improve this situation you have been advised to consider how effective testing can be achieved by making provision at the design stage. In particular you should:

? Partition complex circuits to reduce testing effort.

? Maximise access to inputs and outputs of complex devices so that the ICT can exert control and observe effects.

You already know that not all faults can be detected with one tester, hence your investigation into ICTs, MDAs and FTs. However, test equipment and its ongoing use cost money and it is important that testing is carried out economically as well as effectively. To specify capacities for your different testers will require more than knowledge of your overall unit throughput. You need to develop a test strategy that takes into account the effects of yield and ‘fault spectrum’ as well as purchase and running costs.

Guidance notes

Remember you do not necessarily have to solve the problem described. You do, however, need to understand and be able to explain how you would approach the problem.

Learning Outcomes

Following this PBL cycle you should be able to:

? Explain why design should take into account testing requirements.
? Discuss the use of partitioning to reduce test effort required.
? Describe methods for ensuring controllability and observability when designing circuits for test.
? Design an optimum test configuration (with equipment capacities) given information about product yield and fault spectrum.

Resources

Library Catalogue

? Automatic Test Equipment Brindley
? Testing Digital Circuits B.R.Wilkins
? Advanced Simulation &Test Methodologies for VLSI Russel & Sayers
? IEEE Standard 1149.1
? The Low Cost Board Test Handbook Craig Pynn
? Strategies for Electronic Test Craig Pynn
? Digital Board Testing Bennets
? Design to Test Turino

Internet
http://www.checksum.com/analyst_ft.html

Design for Test 2
Following your initial investigation into test equipment and its use you have become aware that increasing use of VLSI and SMT technology means that not all component faults can be detected with an In Circuit Tester. To improve this situation you have been advised to consider how effective testing can be achieved by making provision at the design stage. In particular you should:

? Partition complex circuits to reduce testing effort.

? Maximise access to inputs and outputs of complex devices so that the ICT can exert control and observe effects.

You already know that not all faults can be detected with one tester, hence your investigation into ICTs, MDAs and FTs. However, test equipment and its ongoing use cost money and it is important that testing is carried out economically as well as effectively. To specify capacities for your different testers will require more than knowledge of your overall unit throughput. You need to develop a test strategy that takes into account the effects of yield and ‘fault spectrum’ as well as purchase and running costs.

Guidance notes

Remember you do not necessarily have to solve the problem described. You do, however, need to understand and be able to explain how you would approach the problem.

Learning Outcomes

Following this PBL cycle you should be able to:

? Explain why design should take into account testing requirements.
? Discuss the use of partitioning to reduce test effort required.
? Describe methods for ensuring controllability and observability when designing circuits for test.
? Design an optimum test configuration (with equipment capacities) given information about product yield and fault spectrum.

Resources

Library Catalogue

? Automatic Test Equipment Brindley
? Testing Digital Circuits B.R.Wilkins
? Advanced Simulation &Test Methodologies for VLSI Russel & Sayers
? IEEE Standard 1149.1
? The Low Cost Board Test Handbook Craig Pynn
? Strategies for Electronic Test Craig Pynn
? Digital Board Testing Bennets
? Design to Test Turino

Internet
http://www.checksum.com/analyst_ft.html